Design of Noise - Robust Clock and Data Recovery Using an Adaptive

As the continuing technology scaling keeps increasing the maximum on-chip clock frequency, the demand for the high-speed link that bridges the faster on-chip world and slower off-chip world is rapidly growing. The challenges are stronger than before with more functions being integrated into a single chip, which has become a complicated mixed-mode System on Chip (SoC) design. The performance of the link system greatly depends on how well the noise is managed in the system. Unfortunately the noise conditions in a highly-integrated SoC are usually difficult to predict before chip fabrication and vary quite a lot among different systems. The noise problem is particularly more troublesome on the receiver side than the transmitter side, because the receiver usually consists of more circuit blocks than the transmitter. If one can design a noise-robust receiver that can adapt to various noise conditions, such a macro can be used within a variety of systems and therefore reduce the cost of custom design. This dissertation presents a receiver design that can adjust itself under time-varying noise conditions in order to minimize jitter and achieve optimum performance. This dissertation first describes an adaptive-bandwidth mixed PLL/DLL (MXPDLL)-based multiphase clock generator to achieve the optimum jitter performance